TY - JOUR
T1 - Self-Packaged Compact Filter Array
T2 - Innovations Based on Modified Substrate Integrated Suspension Line Technology
AU - Tang, Tao
AU - Zhang, Runlin
AU - Aldhaeebi, Maged A.
AU - Almoneef, Thamer S.
N1 - Publisher Copyright:
© 2011-2012 IEEE.
PY - 2025
Y1 - 2025
N2 - This article introduces a novel approach to designing a self-packaged filter array by integrating two bandpass filters (BPFs) onto a substrate integrated suspended line (SISL) platform. The innovative topology employed in this design establishes individual air cavities for each filter circuit, created by layering multiple substrate layers and packaging them with grounded substrates at both ends. All filter input and output ports are situated on the bottom ground plane and are connected to their respective ports via metal pins and a multilayer substrate. To address impedance-matching challenges and mitigate parasitic effects resulting from the metal pin connections, strategic impedance-matching techniques are implemented at the pin-to-microstrip line junctions. Furthermore, vertical interconnect access (VIA) structures are strategically positioned around the periphery of the air cavities, linking the ground planes of all substrate layers. This design innovation reduces the number of air cavities by two compared to conventional SISL structures, effectively minimizing volume and shortening connection pin lengths, thereby simplifying the impedance-matching process. The design achieves a quad-flat no-leads (QFN) packaging style by encapsulating each filter circuit with a multilayer substrate containing ground planes, VIAs, and top and bottom ground layers. Validation of the proposed packaging design concept is conducted experimentally through the measurement of two BPFs, with results indicating that the proposed packaging mode enhances filter performance, particularly in terms of reducing losses.
AB - This article introduces a novel approach to designing a self-packaged filter array by integrating two bandpass filters (BPFs) onto a substrate integrated suspended line (SISL) platform. The innovative topology employed in this design establishes individual air cavities for each filter circuit, created by layering multiple substrate layers and packaging them with grounded substrates at both ends. All filter input and output ports are situated on the bottom ground plane and are connected to their respective ports via metal pins and a multilayer substrate. To address impedance-matching challenges and mitigate parasitic effects resulting from the metal pin connections, strategic impedance-matching techniques are implemented at the pin-to-microstrip line junctions. Furthermore, vertical interconnect access (VIA) structures are strategically positioned around the periphery of the air cavities, linking the ground planes of all substrate layers. This design innovation reduces the number of air cavities by two compared to conventional SISL structures, effectively minimizing volume and shortening connection pin lengths, thereby simplifying the impedance-matching process. The design achieves a quad-flat no-leads (QFN) packaging style by encapsulating each filter circuit with a multilayer substrate containing ground planes, VIAs, and top and bottom ground layers. Validation of the proposed packaging design concept is conducted experimentally through the measurement of two BPFs, with results indicating that the proposed packaging mode enhances filter performance, particularly in terms of reducing losses.
KW - Filter-array
KW - impedance matching
KW - modified substrate integrated suspended line (SISL)
KW - multilayer substrate
KW - self-packaged
UR - http://www.scopus.com/inward/record.url?scp=105001243312&partnerID=8YFLogxK
U2 - 10.1109/TCPMT.2025.3554181
DO - 10.1109/TCPMT.2025.3554181
M3 - Article
AN - SCOPUS:105001243312
SN - 2156-3950
VL - 15
SP - 1025
EP - 1031
JO - IEEE Transactions on Components, Packaging and Manufacturing Technology
JF - IEEE Transactions on Components, Packaging and Manufacturing Technology
IS - 5
ER -