Reconfigurable Hardware Accelerator for Profile Hidden Markov Models

We propose a processor array accelerator for profile hidden Markov models of the Viterbi algorithm. The proposed processor array has the advantage that it can be modified to enable hardware reuse rather than replicating processing elements of the processor array on a cluster of FPGAs. Also, it has the advantage of reducing the area overhead of the FPGA compared to the previously published conventional processor arrays. This allows for increasing the number of processing elements and the system throughput. The proposed processor array and the previously reported conventional one are coded using the VHDL language and implemented using the FPGA technology. The implementation results showed that the proposed design achieves 1.31× to 1.75×speedup and saves area ranging from 24.4 to 34.0% over the conventional design for profile HMM query lengths ranging from 38 to 2295.