Enhanced FPGA implementation of the SHA-512 hash function

In modern cryptographic hash function plays an important role. Hash function algorithms are widely used to provide authentication, security and services of integrity. The main computation block in SHA-512 algorithm is governed by a loop with high data dependence for which one implementation strategy is explored in this work as well as design efficiently mapped to hardware architecture. We propose an improved implementation of the SHA-512 hash family, with minimal operator latency, reduced hardware requirements, high frequency, and high throughput. The proposed design were implemented and validated in the FPGA Virtex. The FPGAs targets are XC5VLX30-3ff324, XC6VLX75T-3ff784.