Efficient FPGA hardware implementation of secure hash function SHA-256/Blake-256

Fatma Kahri; Hassen Mestiri; Belgacem Bouallegue; Mohsen Machhout

doi:10.1109/SSD.2015.7348105

Efficient FPGA hardware implementation of secure hash function SHA-256/Blake-256

Fatma Kahri, Hassen Mestiri, Belgacem Bouallegue, Mohsen Machhout

University of Monastir

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

15 Scopus citations

Abstract

: Since the beginning of study of the Secure Hash function (SHA), it has been thoroughly studied by designers with the goal of reducing the area, frequency, and throughput of the hardware implementation of this cryptosystem. The Secure Hash function algorithm has become the default choice for security services in numerous applications. In this paper, we proposed a new design for the SHA-256 and blake-256 functions. Moreover, the proposed design has been implemented on Xilinx Virtex-5 FPGA. Its area, frequency and throughput have been compared and it is shown that the proposed design achieve good performance in term of area, frequency and throughput.

Original language	English
Title of host publication	12th International Multi-Conference on Systems, Signals and Devices, SSD 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479917587
DOIs	https://doi.org/10.1109/SSD.2015.7348105
State	Published - 4 Dec 2015
Externally published	Yes
Event	12th International Multi-Conference on Systems, Signals and Devices, SSD 2015 - Mahdia, Tunisia Duration: 16 Mar 2015 → 19 Mar 2015

Publication series

Name	12th International Multi-Conference on Systems, Signals and Devices, SSD 2015

Conference

Conference	12th International Multi-Conference on Systems, Signals and Devices, SSD 2015
Country/Territory	Tunisia
City	Mahdia
Period	16/03/15 → 19/03/15

Keywords

Blake-256
FPGA Implementation
Security
SHA-256

Access to Document

10.1109/SSD.2015.7348105

Cite this

Kahri, F., Mestiri, H., Bouallegue, B., & Machhout, M. (2015). Efficient FPGA hardware implementation of secure hash function SHA-256/Blake-256. In 12th International Multi-Conference on Systems, Signals and Devices, SSD 2015 Article 7348105 (12th International Multi-Conference on Systems, Signals and Devices, SSD 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SSD.2015.7348105

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abstract = ": Since the beginning of study of the Secure Hash function (SHA), it has been thoroughly studied by designers with the goal of reducing the area, frequency, and throughput of the hardware implementation of this cryptosystem. The Secure Hash function algorithm has become the default choice for security services in numerous applications. In this paper, we proposed a new design for the SHA-256 and blake-256 functions. Moreover, the proposed design has been implemented on Xilinx Virtex-5 FPGA. Its area, frequency and throughput have been compared and it is shown that the proposed design achieve good performance in term of area, frequency and throughput.",

keywords = "Blake-256, FPGA Implementation, Security, SHA-256",

author = "Fatma Kahri and Hassen Mestiri and Belgacem Bouallegue and Mohsen Machhout",

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Kahri, F, Mestiri, H, Bouallegue, B & Machhout, M 2015, Efficient FPGA hardware implementation of secure hash function SHA-256/Blake-256. in 12th International Multi-Conference on Systems, Signals and Devices, SSD 2015., 7348105, 12th International Multi-Conference on Systems, Signals and Devices, SSD 2015, Institute of Electrical and Electronics Engineers Inc., 12th International Multi-Conference on Systems, Signals and Devices, SSD 2015, Mahdia, Tunisia, 16/03/15. https://doi.org/10.1109/SSD.2015.7348105

Efficient FPGA hardware implementation of secure hash function SHA-256/Blake-256. / Kahri, Fatma; Mestiri, Hassen; Bouallegue, Belgacem et al.
12th International Multi-Conference on Systems, Signals and Devices, SSD 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7348105 (12th International Multi-Conference on Systems, Signals and Devices, SSD 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Mestiri, Hassen

AU - Bouallegue, Belgacem

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Y1 - 2015/12/4

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AB - : Since the beginning of study of the Secure Hash function (SHA), it has been thoroughly studied by designers with the goal of reducing the area, frequency, and throughput of the hardware implementation of this cryptosystem. The Secure Hash function algorithm has become the default choice for security services in numerous applications. In this paper, we proposed a new design for the SHA-256 and blake-256 functions. Moreover, the proposed design has been implemented on Xilinx Virtex-5 FPGA. Its area, frequency and throughput have been compared and it is shown that the proposed design achieve good performance in term of area, frequency and throughput.

KW - Blake-256

KW - FPGA Implementation

KW - Security

KW - SHA-256

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M3 - Conference contribution

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T3 - 12th International Multi-Conference on Systems, Signals and Devices, SSD 2015

BT - 12th International Multi-Conference on Systems, Signals and Devices, SSD 2015

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Kahri F, Mestiri H, Bouallegue B, Machhout M. Efficient FPGA hardware implementation of secure hash function SHA-256/Blake-256. In 12th International Multi-Conference on Systems, Signals and Devices, SSD 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7348105. (12th International Multi-Conference on Systems, Signals and Devices, SSD 2015). doi: 10.1109/SSD.2015.7348105

Efficient FPGA hardware implementation of secure hash function SHA-256/Blake-256

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Keywords

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