Buffers sharing switch design exploiting dynamic traffic orientation in a NoC

Manel Lanzar, Riadh Bourguiba, Jaouhar Mouine

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Global interconnects are the main performance bottleneck for nowadays complex Systems on Chip. The Network on chip paradigm is a new interconnection solution outperforming the bus based on chip interconnects. Many studies focused on the improvement of NoC performances in terms of latency, throughput and power consumption. In this paper, a new switch architecture addressing the problem of buffers underutilization is proposed. It enables the exploitation of traffic patterns orientation by adaptively sharing free virtual channels among different input ports. This switch improves the latency and throughput performances.

Original languageEnglish
Title of host publication2018 15th International Multi-Conference on Systems, Signals and Devices, SSD 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1032-1036
Number of pages5
ISBN (Electronic)9781538653050
DOIs
StatePublished - 7 Dec 2018
Event15th International Multi-Conference on Systems, Signals and Devices, SSD 2018 - Yassmine, Hammamet, Tunisia
Duration: 19 Mar 201822 Mar 2018

Publication series

Name2018 15th International Multi-Conference on Systems, Signals and Devices, SSD 2018

Conference

Conference15th International Multi-Conference on Systems, Signals and Devices, SSD 2018
Country/TerritoryTunisia
CityYassmine, Hammamet
Period19/03/1822/03/18

Keywords

  • Inter ports buffers sharing
  • Network on Chip
  • Traffic pattern
  • Virtual channel

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