A New Design Optimization Methodology of Fully Differential Dynamic Comparator

The need to reduce the time to market for high-performance integrated circuits has become a primary concern in modern electronics design. Many efforts are currently being made to streamline the design process for increasing complexity circuits while providing optimal performances, especially for nanoscale technologies. This paper presents a new and effective methodology for the design of fully differential comparators to achieve a high-performance operation using dynamic topology and nanoscale technology. The proposed methodology is not process dependent and can be applied to similar conventional comparator structures to optimize the operation speed while ensuring good offset cancellation, efficient noise immunity, and reduced design time and complexity. The design steps include theoretical analysis and simulation-based optimization of the comparator speed, as well as offset and noise reduction within a minimal design time. All the analog and digital building blocks are designed using dynamic topologies, including the clock generator, to ensure high speed and synchronized operation. The resulting circuit is a new two-stage dual clock fully differential comparator. Compared with its equivalent counterparts, it provides improved operation speed, and reduced offset voltage and kickback noise. This comparator is designed in the TSMC 65 nm CMOS process. Its performance shows that it achieves a 1.25 GHz operation speed, presents less than 9 mV offset error, and generates a kickback noise of less than 40 mV with a 10 kΩ input resistance during the reset phase only. It consumes 213 µW from a 1.2 V power supply at 1.25 GHz.