A Low Impedance Current-Reuse Path for UWB-PA to Improve Efficiency and Gain

Current-reuse circuit with a low impedance current-reuse path has been proposed to enrich high flat gain, high efficiency, and high output power across the operating band. While an inductor-capacitor (LC) interstage is employed to improve the linearity of the proposed PA. In the second stage, the shunt peaking design in a common-source circuit is employed to improve the power gain, while a network of reactance compensation is adopted at the output of the second stage to overcome the parasitic capacitance's impact on the active device. The post-layout simulation using the TSMC 65 nm CMOS process is carried out on the entire frequency range from 3.1 GHz to 10.6 GHz. The post-layout simulation achieved ±42 ps group delay variation, 32% power-added efficiency (PAE), and 32-dB power gain. Matching input and output of less than −10 dB has been achieved over the operating band, and it achieved an output power of 18.3 dBm.