A 7L and 11L High Step-Up SCMLI Topology With Reduced Component Voltage Stress

Jagabar Sathik Mohamed Ali; Amjad Rehman Khan; Gopinath Narayanan Pandurangan; Prem Ponnusamy; Faten S. Alamri; Saeed Ali Bahaj

doi:10.1109/ACCESS.2023.3333363

A 7L and 11L High Step-Up SCMLI Topology With Reduced Component Voltage Stress

Jagabar Sathik Mohamed Ali, Amjad Rehman Khan, Gopinath Narayanan Pandurangan, Prem Ponnusamy, Faten S. Alamri, Saeed Ali Bahaj

Management Information Systems

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

This article proposes a new capacitor-based multilevel inverter topology (CBMLI) with fewer devices and reduced voltage stress on capacitors and switches. In addition, the proposed topology can be configured as either a 7-level (7L) or 11L circuit with a maximum voltage gain of 3 and 2.5 times, respectively. Comparisons are made between the proposed topology and existing recent CBMLI topologies, and various power loss analyses are presented. The capacitance values are determined by selecting the maximum discharging period, and the associated analysis is presented. Using the simulation software MATLAB/Simulink, the performance of the proposed circuit topology is validated, and the same is tested in the hardware setup. The various dynamic performance characteristics, such as loading changes, input variations, and modulation index, are validated, and the resulting data is discussed.

Original language	English
Pages (from-to)	139785-139797
Number of pages	13
Journal	IEEE Access
Volume	11
DOIs	https://doi.org/10.1109/ACCESS.2023.3333363
State	Published - 2023

Keywords

multilevel inverter
Switched capacitor
technological development
voltage boost

Access to Document

10.1109/ACCESS.2023.3333363

Cite this

@article{7480a82d186f462c97fc0fc4a7c4d705,

title = "A 7L and 11L High Step-Up SCMLI Topology With Reduced Component Voltage Stress",

abstract = "This article proposes a new capacitor-based multilevel inverter topology (CBMLI) with fewer devices and reduced voltage stress on capacitors and switches. In addition, the proposed topology can be configured as either a 7-level (7L) or 11L circuit with a maximum voltage gain of 3 and 2.5 times, respectively. Comparisons are made between the proposed topology and existing recent CBMLI topologies, and various power loss analyses are presented. The capacitance values are determined by selecting the maximum discharging period, and the associated analysis is presented. Using the simulation software MATLAB/Simulink, the performance of the proposed circuit topology is validated, and the same is tested in the hardware setup. The various dynamic performance characteristics, such as loading changes, input variations, and modulation index, are validated, and the resulting data is discussed.",

keywords = "multilevel inverter, Switched capacitor, technological development, voltage boost",

author = "Ali, \{Jagabar Sathik Mohamed\} and Khan, \{Amjad Rehman\} and Pandurangan, \{Gopinath Narayanan\} and Prem Ponnusamy and Alamri, \{Faten S.\} and Bahaj, \{Saeed Ali\}",

note = "Publisher Copyright: {\textcopyright} 2013 IEEE.",

year = "2023",

doi = "10.1109/ACCESS.2023.3333363",

language = "English",

volume = "11",

pages = "139785--139797",

journal = "IEEE Access",

issn = "2169-3536",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - A 7L and 11L High Step-Up SCMLI Topology With Reduced Component Voltage Stress

AU - Ali, Jagabar Sathik Mohamed

AU - Khan, Amjad Rehman

AU - Pandurangan, Gopinath Narayanan

AU - Ponnusamy, Prem

AU - Alamri, Faten S.

AU - Bahaj, Saeed Ali

PY - 2023

Y1 - 2023

N2 - This article proposes a new capacitor-based multilevel inverter topology (CBMLI) with fewer devices and reduced voltage stress on capacitors and switches. In addition, the proposed topology can be configured as either a 7-level (7L) or 11L circuit with a maximum voltage gain of 3 and 2.5 times, respectively. Comparisons are made between the proposed topology and existing recent CBMLI topologies, and various power loss analyses are presented. The capacitance values are determined by selecting the maximum discharging period, and the associated analysis is presented. Using the simulation software MATLAB/Simulink, the performance of the proposed circuit topology is validated, and the same is tested in the hardware setup. The various dynamic performance characteristics, such as loading changes, input variations, and modulation index, are validated, and the resulting data is discussed.

AB - This article proposes a new capacitor-based multilevel inverter topology (CBMLI) with fewer devices and reduced voltage stress on capacitors and switches. In addition, the proposed topology can be configured as either a 7-level (7L) or 11L circuit with a maximum voltage gain of 3 and 2.5 times, respectively. Comparisons are made between the proposed topology and existing recent CBMLI topologies, and various power loss analyses are presented. The capacitance values are determined by selecting the maximum discharging period, and the associated analysis is presented. Using the simulation software MATLAB/Simulink, the performance of the proposed circuit topology is validated, and the same is tested in the hardware setup. The various dynamic performance characteristics, such as loading changes, input variations, and modulation index, are validated, and the resulting data is discussed.

KW - multilevel inverter

KW - Switched capacitor

KW - technological development

KW - voltage boost

UR - http://www.scopus.com/inward/record.url?scp=85178021698&partnerID=8YFLogxK

U2 - 10.1109/ACCESS.2023.3333363

DO - 10.1109/ACCESS.2023.3333363

M3 - Article

AN - SCOPUS:85178021698

SN - 2169-3536

VL - 11

SP - 139785

EP - 139797

JO - IEEE Access

JF - IEEE Access

ER -

A 7L and 11L High Step-Up SCMLI Topology With Reduced Component Voltage Stress

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this