TY - GEN
T1 - A 0.95-to-5.28 GHz Fast Locking and Power Efficient Digital Phase Locked Loop
AU - Mohammed, Reham I.A.
AU - Abdelghany, Mahmoud A.
AU - Khalaf, Ashraf A.M.
AU - Hamed, Hesham F.A.
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - Computers, radios, televisions, and mobile phones are only a few examples of devices that depend on phase-locked loops (PLLs). PLL development is an extraordinarily complex process as it involves different parameters, and it is difficult to optimize all these parameters to get better performance. Depending on the application in which the PLL is used, we tend to improve some issues at the expense of others. The proposed Digital PLL (DPLL) is designed with a current-controlled ring oscillator (CCRO) which consumes low power and has a small locking time and operates over a wide range compared to other Digitally Controlled Oscillators (DCOs). The proposed architecture is implemented in a TSMC 65 nm CMOS process. It can generate an output frequency from 0.95 to 5.28 GHz and operates across a supply voltage range of 0.6 V to 1.2 V. At 0.9 V supply voltage the output frequency is about 3.091 GHz and the PLL consumes 50.3 μw with locking time 79.3 ns.
AB - Computers, radios, televisions, and mobile phones are only a few examples of devices that depend on phase-locked loops (PLLs). PLL development is an extraordinarily complex process as it involves different parameters, and it is difficult to optimize all these parameters to get better performance. Depending on the application in which the PLL is used, we tend to improve some issues at the expense of others. The proposed Digital PLL (DPLL) is designed with a current-controlled ring oscillator (CCRO) which consumes low power and has a small locking time and operates over a wide range compared to other Digitally Controlled Oscillators (DCOs). The proposed architecture is implemented in a TSMC 65 nm CMOS process. It can generate an output frequency from 0.95 to 5.28 GHz and operates across a supply voltage range of 0.6 V to 1.2 V. At 0.9 V supply voltage the output frequency is about 3.091 GHz and the PLL consumes 50.3 μw with locking time 79.3 ns.
KW - Analog PLL (APLL)
KW - Current Controlled Ring Oscillator (CCRO)
KW - Digital PLL (DPLL)
KW - Phase Frequency Detector (PFD)
KW - Phase Locked Loop (PLL)
UR - http://www.scopus.com/inward/record.url?scp=85144593794&partnerID=8YFLogxK
U2 - 10.1109/NRSC57219.2022.9971314
DO - 10.1109/NRSC57219.2022.9971314
M3 - Conference contribution
AN - SCOPUS:85144593794
T3 - National Radio Science Conference, NRSC, Proceedings
SP - 264
EP - 272
BT - Proceedings of 2022 39th National Radio Science Conference, NRSC 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 39th National Radio Science Conference, NRSC 2022
Y2 - 29 November 2022 through 1 December 2022
ER -