Scalable and Parameterizable Processor Array Architecture for Similarity Distance Computation

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Abstract

Processor array architecture is a popular approach to improve computation of similarity distance matrices; however, most of the proposed architectures are designed in an ad hoc manner, some have not even considered dimensionality and size of the datasets. We believe a systematic approach is necessary to explore the design space. In this work, we present a technique for designing scalable processor array architecture for the similarity distance matrix computation. Implementation results of the proposed architecture show improved compromise between area and speed. Moreover, it scales better for large and high-dimensional datasets since the architecture is fully parameterized and only has to deal with one data dimension in each time step.

Original languageEnglish
Title of host publication2019 10th International Conference on Information and Communication Systems, ICICS 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages245-249
Number of pages5
ISBN (Electronic)9781728100456
DOIs
StatePublished - Jun 2019
Event10th International Conference on Information and Communication Systems, ICICS 2019 - Irbid, Jordan
Duration: 11 Jun 201913 Jun 2019

Publication series

Name2019 10th International Conference on Information and Communication Systems, ICICS 2019

Conference

Conference10th International Conference on Information and Communication Systems, ICICS 2019
Country/TerritoryJordan
CityIrbid
Period11/06/1913/06/19

Keywords

  • parallel computing.
  • Processor arrays
  • scalable hardware
  • similarity measures

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