TY - GEN
T1 - Proposed unified 32-bit multiplier/inverter for asymmetric cryptography
AU - Sghaier, Anissa
AU - Zeghid, Medien
AU - Massoud, Chiraz
AU - MacHhout, Mohsen
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2017/6/5
Y1 - 2017/6/5
N2 - Arithmetic in GF(2n) finite fields in asymmetric cryptography is the key of an efficient cryptosystems implementation. Thus, cryptosystems based on algebraic curves such as Hyper/Elliptic curves (ECC,HECC) and Pairings need a big number of arithmetic operations. They required several GF(2n) inversions and multiplications which are the most time and area consuming operations. This paper describes a hardware architecture for computing both modular multiplication and modular inversion in GF(2n) finite fields, based on a Modified Serial Multiplication/Inversion (MSMI) algorithm. The algorithm is suitable for both hardware implementations and software implementations. The proposed design performs 8-bits, 16-bits, 32-bits or 64-bits modular multiplication or inversion. Our design was modeled using VHDL and implemented in the Xilinx FPGAs Virtex6. Implementation results prove that our MSMI uses only 219 FPGA slices, it achieves a maximum frequency of 150 MHz and it computes 163-bits modular multiplication in 4.21 μ secs.
AB - Arithmetic in GF(2n) finite fields in asymmetric cryptography is the key of an efficient cryptosystems implementation. Thus, cryptosystems based on algebraic curves such as Hyper/Elliptic curves (ECC,HECC) and Pairings need a big number of arithmetic operations. They required several GF(2n) inversions and multiplications which are the most time and area consuming operations. This paper describes a hardware architecture for computing both modular multiplication and modular inversion in GF(2n) finite fields, based on a Modified Serial Multiplication/Inversion (MSMI) algorithm. The algorithm is suitable for both hardware implementations and software implementations. The proposed design performs 8-bits, 16-bits, 32-bits or 64-bits modular multiplication or inversion. Our design was modeled using VHDL and implemented in the Xilinx FPGAs Virtex6. Implementation results prove that our MSMI uses only 219 FPGA slices, it achieves a maximum frequency of 150 MHz and it computes 163-bits modular multiplication in 4.21 μ secs.
KW - hardware architecture
KW - modular inversion
KW - Modular multiplication
KW - MSMI
UR - https://www.scopus.com/pages/publications/85021406214
U2 - 10.1109/SETIT.2016.7939851
DO - 10.1109/SETIT.2016.7939851
M3 - Conference contribution
AN - SCOPUS:85021406214
T3 - 2016 7th International Conference on Sciences of Electronics, Technologies of Information and Telecommunications, SETIT 2016
SP - 109
EP - 112
BT - 2016 7th International Conference on Sciences of Electronics, Technologies of Information and Telecommunications, SETIT 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th International Conference on Sciences of Electronics, Technologies of Information and Telecommunications, SETIT 2016
Y2 - 18 December 2016 through 20 December 2016
ER -