Pipeline hazards resolution for a new programmable instruction set RISC processor

The work presented in this paper is a part of a project that aims to concept and implement a hardwired programmable processor. A 32-bit RISC processor with customizable ALU (Arithmetic and Logic Unit) is designed then the pipeline technique is implemented is order to reach better performances. However the use of this technique can lead to several troubles called hazards that can affect the correct execution of the program. In this context, this paper identifies and analyzes all different hazards that can occur in this processor pipeline stages. Then detailed solutions are proposed, implemented and validated.