Multi-level AES design security: From SystemC-TLM to FPGA

Advanced Encryption Standard (AES) cryptographic system are widely used in embedded systems to secure secret information. One of the most powerful cryptanalysis techniques against the cryptographic systems is the fault injection attacks. The complexity of cryptographic systems is increasing which requires fast security attacks simulation against fault injection attacks. The multi-level Electronic System Level approach is one promising candidate that allows models to reach higher simulation speed. It is known that the SystemC Transaction Level Modeling (TLM) package simulates models 1000 times higher than classical Register Transfer Level (RTL) simulators. In this paper, we present a secure reconfigurable AES design against the fault injection attacks at the Electronic System Level. Simulation results demonstrate that the simulation time is dependent of the fault detection schemes types. Moreover, The SystemC design is refined to RTL level. It is translated from SystemC description to a VHDL equivalent and implemented on Xilinx Virtex-5 FPGA. Experimental synthesis results show that the secure reconfigurable AES design is very robust against fault injection attacks and the fault detection scheme information redundancy allows a trade-off between the hardware overhead and the security against fault injection attacks.