@inproceedings{648b0b1539bd4dd7814ad7982c05b0f9,
title = "Low power 1-Bit full adder using Full-Swing gate diffusion input technique",
abstract = "This paper presents a design which provides full swing output for logic 1 and logic 0 for 1-bit full adder cell and reduces power consumption, delay, and area. In this design full adder consists of two XOR gate cells and one cell of 2×1 multiplexer (MUX). The performance of the proposed design compared with the different logic style for full adders through cadence virtuoso simulation based on TSMC 65nm technology models with a supply voltage of 1v and frequency 125MHz. The simulation results showed that the proposed full adder design dissipates low power, while improving delay and area among all the design taken for comparison.",
keywords = "FS-GDI, Full adder, Gate Diffusion Input (GDI)",
author = "Badry, \{Omnia Al\} and Abdelghany, \{M. A.\}",
note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 International Conference on Innovative Trends in Computer Engineering, ITCE 2018 ; Conference date: 19-02-2018 Through 21-02-2018",
year = "2018",
month = mar,
day = "14",
doi = "10.1109/ITCE.2018.8316625",
language = "English",
series = "Proceedings of 2018 International Conference on Innovative Trends in Computer Engineering, ITCE 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "205--208",
booktitle = "Proceedings of 2018 International Conference on Innovative Trends in Computer Engineering, ITCE 2018",
address = "United States",
}