@inproceedings{dafd7a82707045c9a54297baa08e91c1,
title = "Lightweight Hardware Architectures for the Piccolo Block Cipher in FPGA",
abstract = "The Piccolo block cipher is a lightweight block encryption for hardware use. Hardware devices are equipped with limited computation resources and small memory. In this paper, we propose an implementation to carry out through several trade-offs between area and speed. We implemented the Piccolo block cipher algorithm with 128-bit key in two different architectures on FPGA: the iterative and the 4-bit serial architectures. The proposed implementation was performed on Xilinx Spartan-3. The iterative implementation achieves 76\% of resource utilization. This implementation takes 31 clock cycles to perform the encryption or decryption. So, it results in a throughput of 151.1 Mbps. The serial implementation was optimized in terms of area to reduce the cost. It achieves 54\% of resource utilization and takes 496 clock cycles resulting in a throughput of 6.39 Mbps.",
keywords = "Cryptography, FPGA, Hardware architectures, lightweight block cipher, low area, Piccolo block cipher, VHDL",
author = "Ayoub Mhaouch and Wajdi Elhamzi and Mohamed Atri",
note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 5th International Conference on Advanced Technologies for Signal and Image Processing, ATSIP 2020 ; Conference date: 02-09-2020 Through 05-09-2020",
year = "2020",
month = sep,
doi = "10.1109/ATSIP49331.2020.9231586",
language = "English",
series = "2020 International Conference on Advanced Technologies for Signal and Image Processing, ATSIP 2020",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2020 International Conference on Advanced Technologies for Signal and Image Processing, ATSIP 2020",
address = "United States",
}