FPGA implementation of radix 2 division with over-redundant quotient selection

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Abstract

The flexibility of field programmable gate arrays (FPGAs) can provide arithmetic intensive applications with the benefites of custom hardware but without the high cost of custom silicon implementations. In this paper present the adaptation of radix 2 division algorithm for lookup table based FPGAs implementation. This division algorithm is well suited for IEEE 754 standard operands belonging to the range. The implementation has been done with xilinx technology and FPGA-Advantage CAD tools.

Original languageEnglish
Title of host publicationProceedings of the 15th International Conference on Microelectronics, ICM 2003
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages269-273
Number of pages5
ISBN (Electronic)9770520101
DOIs
StatePublished - 2003
Externally publishedYes
Event15th International Conference on Microelectronics, ICM 2003 - Cairo, Egypt
Duration: 9 Dec 200311 Dec 2003

Publication series

NameProceedings of the International Conference on Microelectronics, ICM
Volume2003-January

Conference

Conference15th International Conference on Microelectronics, ICM 2003
Country/TerritoryEgypt
CityCairo
Period9/12/0311/12/03

Keywords

  • Application software
  • Arithmetic
  • Circuits
  • Costs
  • Fabrication
  • Field programmable gate arrays
  • Hardware
  • Logic
  • Silicon
  • Table lookup

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