FPGA implementation of fast radix 4 division algorithm

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4 Scopus citations

Abstract

The flexibility of field programable gate arrays (FPGAs) can provide arithmetic intensive applications with the benefites of custom hardware but without the high cost of custom silicon implementations. In this paper, we present the adaptation of a fast radix 4 division algorithm for lookup table based FPGAs implementation. In this algorithm, the quotient digits are determined by observing three most-significant radix 2 digits of the partial remainder and independent of the divisor. The implementation has been done with Xilinx technology and FPGA-Advantage CAD tools.

Original languageEnglish
Title of host publicationProceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004
EditorsW. Badawy, Y. Ismail
Pages69-72
Number of pages4
DOIs
StatePublished - 2004
Externally publishedYes
EventProceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004 - Banff, Alta, Canada
Duration: 19 Jul 200421 Jul 2004

Publication series

NameProceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004

Conference

ConferenceProceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004
Country/TerritoryCanada
CityBanff, Alta
Period19/07/0421/07/04

Keywords

  • Fast division
  • Field programmable gate arrays (FPGAs)
  • Quotient selection
  • Radix 4 division

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