Efficient Parallel and Serial Systolic Structures for Multiplication and Squaring over GF(2m )

In this paper, we present efficient parallel and serial systolic structures for combined multiplication and squaring over GF( 2m ). The proposed structures have the advantage of computing both modular multiplication and squaring simultaneously for fast execution of modular exponentiation. They share the same hardware components for both operations and this gives them the advantage of saving more space than the case of using a separate structure for each operation. In addition, they have a regular structure and local communication between the processing elements and this makes them more efficient for VLSI implementation. Complexity analysis of the proposed designs and the existing most recent and efficient designs indicates that the proposed serial design has 31.7% lower area-time (AT) complexity than the previously reported most recent serial one. In addition, the proposed parallel design has a significant lower AT complexity over the recent efficient parallel designs by at least 96.9%.