TY - GEN
T1 - Efficient hardware multiplier design for pairing computation
AU - Massoud, Chiraz
AU - Sghaier, Anissa
AU - Zeghid, Medien
AU - Machhout, Mohssen
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2016/7/5
Y1 - 2016/7/5
N2 - In Public Key Cryptography, the most costly arithmetic operation is first inversion then multiplication. There aren't big researches concerning modular inversion, it exist two famous algorithms which are Fermat and Extended Euclid algorithms. All researches are oriented to the modular multiplier, it exist a big number of methods to compute it. The goal of our paper is to present a of a 256-bits multiplier design, to compute pairings at security level of 128-bits. Our hardware architecture exploits FPGA features (Fast Carry Chain and DSP), for this reason, it's less constrained in memory and power consumption. These performances prove the limitations of the restrained environment. Our design is coded in VHDL language and synthesized using Xilinx ISE 14.5 on Virtex 6 FPGA XC6VLX240T devices. Our multiplier used only 1665 slices and 3 DSP, it runs at 149.8 MHz clock frequency.
AB - In Public Key Cryptography, the most costly arithmetic operation is first inversion then multiplication. There aren't big researches concerning modular inversion, it exist two famous algorithms which are Fermat and Extended Euclid algorithms. All researches are oriented to the modular multiplier, it exist a big number of methods to compute it. The goal of our paper is to present a of a 256-bits multiplier design, to compute pairings at security level of 128-bits. Our hardware architecture exploits FPGA features (Fast Carry Chain and DSP), for this reason, it's less constrained in memory and power consumption. These performances prove the limitations of the restrained environment. Our design is coded in VHDL language and synthesized using Xilinx ISE 14.5 on Virtex 6 FPGA XC6VLX240T devices. Our multiplier used only 1665 slices and 3 DSP, it runs at 149.8 MHz clock frequency.
KW - elliptic curve cryptography (ECC)
KW - modular multiplication
KW - Pairing
UR - https://www.scopus.com/pages/publications/84979658421
U2 - 10.1109/STA.2015.7505172
DO - 10.1109/STA.2015.7505172
M3 - Conference contribution
AN - SCOPUS:84979658421
T3 - 16th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering, STA 2015
SP - 117
EP - 120
BT - 16th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering, STA 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 16th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering, STA 2015
Y2 - 21 December 2015 through 23 December 2015
ER -