A scheduling approach for packet-switched on-chip networks

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Performance constraints imposed on the on-Chip System (SoC) design require efficiency and predictability of inter-core communication part in system. This implies the Quality-of-Service (QoS) requirement assurance for the communication. The current work presents a novel approach that borrows three Real-Time Operating System (RTOS) scheduling algorithms and adapts them to Networks-on-Chip (NoCs). This technique is designed specifically for multimedia and safety-critical real-time applications to reduce contention problem in packet-switched networks and provides QoS guarantees in terms of throughput and end-to-end latency. An HDL implementation of a NoC architecture has been simulated to prove our concept.

Original languageEnglish
Title of host publication2011 International Conference on Communications, Computing and Control Applications, CCCA 2011
DOIs
StatePublished - 2011
Externally publishedYes
Event2011 International Conference on Communications, Computing and Control Applications, CCCA 2011 - Hammamet, Tunisia
Duration: 3 Mar 20115 Mar 2011

Publication series

Name2011 International Conference on Communications, Computing and Control Applications, CCCA 2011

Conference

Conference2011 International Conference on Communications, Computing and Control Applications, CCCA 2011
Country/TerritoryTunisia
CityHammamet
Period3/03/115/03/11

Keywords

  • design
  • implementation
  • Network-on-Chip
  • packet scheduling
  • performance
  • Quality-of-Service
  • router

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