A reusable hybrid RISC processor with programmable instruction set

Hajer Najjar, Riad Bourguiba, Jaouhar Mouine

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Embedded systems face several area and power consumption constraints in addition to the real-time challenges. This promotes the use of hard-core processors. However, their rigid instruction sets make them unsuitable for some applications. In this paper we propose a new processor design which adds the programmable aspect to a hardwired processor architecture, so that the reuse possibilities are increased.

Original languageEnglish
Title of host publication2018 15th International Multi-Conference on Systems, Signals and Devices, SSD 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1028-1031
Number of pages4
ISBN (Electronic)9781538653050
DOIs
StatePublished - 7 Dec 2018
Event15th International Multi-Conference on Systems, Signals and Devices, SSD 2018 - Yassmine, Hammamet, Tunisia
Duration: 19 Mar 201822 Mar 2018

Publication series

Name2018 15th International Multi-Conference on Systems, Signals and Devices, SSD 2018

Conference

Conference15th International Multi-Conference on Systems, Signals and Devices, SSD 2018
Country/TerritoryTunisia
CityYassmine, Hammamet
Period19/03/1822/03/18

Keywords

  • embedded systems
  • hard-core
  • LUT
  • processors
  • programmable logic
  • RISC
  • soft-core

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