TY - GEN
T1 - A hardware FPGA implementation of fault attack countermeasure
AU - Mestiri, Hassen
AU - Kahri, Fatma
AU - Bouallegue, Belgacem
AU - Machhout, Mohsen
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2014/4/15
Y1 - 2014/4/15
N2 - To secure the Advanced Encryption Standard (AES) implementation against fault injection attacks known as differential fault analysis attacks, different fault detection schemes have been proposed. The AES is used in many embedded systems to provide security. It has become the default choice for security services in numerous applications. In this paper, a parity fault detection scheme has been presented in order to secure AES. This scheme based on parity comparison between the correct parity of the round output and the predicted parity according to the processing steps of the AES round. Moreover, we discuss the strengths and the weaknesses of this scheme against the fault attacks. Experimental synthesis results show that the fault coverage reaches 99.86% for the proposed scheme. The proposed fault detection scheme has been implemented on Xilinx Virtex-5 FPGA. Its fault coverage, area overhead, frequency degradation and throughput have been compared and it is shown that the proposed scheme allows a trade-off between the implementation cost and the security of the AES.
AB - To secure the Advanced Encryption Standard (AES) implementation against fault injection attacks known as differential fault analysis attacks, different fault detection schemes have been proposed. The AES is used in many embedded systems to provide security. It has become the default choice for security services in numerous applications. In this paper, a parity fault detection scheme has been presented in order to secure AES. This scheme based on parity comparison between the correct parity of the round output and the predicted parity according to the processing steps of the AES round. Moreover, we discuss the strengths and the weaknesses of this scheme against the fault attacks. Experimental synthesis results show that the fault coverage reaches 99.86% for the proposed scheme. The proposed fault detection scheme has been implemented on Xilinx Virtex-5 FPGA. Its fault coverage, area overhead, frequency degradation and throughput have been compared and it is shown that the proposed scheme allows a trade-off between the implementation cost and the security of the AES.
KW - Advanced Encryption Standard
KW - Fault Attacks
KW - Fault Detection
KW - FPGA Implementation
KW - Security
UR - http://www.scopus.com/inward/record.url?scp=84949924429&partnerID=8YFLogxK
U2 - 10.1109/STA.2014.7086674
DO - 10.1109/STA.2014.7086674
M3 - Conference contribution
AN - SCOPUS:84949924429
T3 - STA 2014 - 15th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering
SP - 178
EP - 183
BT - STA 2014 - 15th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 15th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering, STA 2014
Y2 - 21 December 2014 through 23 December 2014
ER -